IS43LD16640C datasheet(75/142 Pages) ISSI

75 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

ZQ External Resistor Value, Tolerance, and Capacitive Loading

To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be connected

between the ZQ pin and ground. A single resistor can be used for each device or one resistor can

be shared between multiple devices if the ZQ calibration timings for each device do not overlap.

The total capacitive loading on the ZQ pin must be limited.

Power-Down

Power-down is entered synchronously when CKE is registered LOW and CS# is HIGH at the ris-

ing edge of clock. A NOP command must be driven in the clock cycle following power-down entry.

CKE must not go LOW while MRR, MRW, READ, or WRITE operations are in progress. CKE can

go LOW while any other operations such as ACTIVATE, PRECHARGE, auto precharge, or RE-

FRESH are in progress, but the power-down IDD specification will not be applied until such opera-

tions are complete.

If power-down occurs when all banks are idle, this mode is referred to as idle power-down;

if power-down occurs when there is a row active in any bank, this mode is referred to as active

power-down.

Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. In

power-down mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW

must be maintained until tCKE is satisfied. VREFCA must be maintained at a valid level during

power-down.

VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned

off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their respective mini-

mum/maximum operating ranges (see AC and DC Operating Conditions).

No refresh operations are performed in power-down mode. The maximum duration in power-down

mode is only limited by the refresh requirements outlined in REFRESH Command.

The power-down state is exited when CKE is registered HIGH. The controller must drive CS# HIGH

in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained

until tCKE is satisfied. A valid, executable command can be applied with power-down exit latency

tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing section.

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