IS43LD16640C datasheet(4/142 Pages) ISSI

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IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

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INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Pad Definition and Description

Name

Type

Description

CK, CK#Input

Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA

inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR)

inputs, CS# and CKE, are sampled at the positive Clock edge.

Clock is defined as the differential pair, CK and CK#. The positive Clock edge is

defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is

defined by the crosspoint of a falling CK and a rising CK#.

CKE

InputClock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and

therefore device input buffers and output drivers. Power savings modes are entered and

exited through CKE transitions.

CKE is considered part of the command code. See Command Truth Table for command

code descriptions.

CKE is sampled at the positive Clock edge.

CS#

Input

Chip Select: CS# is considered part of the command code. See Command Truth Table

for command code descriptions.

CS# is sampled at the positive Clock edge.

CA0 - CA9Input

DDR Command/Address Inputs: Uni-directional command/address bus inputs.

CA is considered part of the command code. See Command Truth Table for command

code descriptions.

DQ0 - DQ15

(x16)

DQ0 - DQ31

(x32)

I/OData Inputs/Output: Bi-directional data bus

DQS0,

DQS0#,

DQS1,

DQS1#

(x16)

DQS0 -

DQS3,

DQS0# -

DQS3#

(x32)

I/O

Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for

read and write data) and differential (DQS and DQS#). It is output with read data and

input with write data. DQS is edge-aligned to read data and centered with write data.

For x16, DQS0 and DQS0# correspond to the data on DQ0 - DQ7; DQS1 and

DQS1# to the data on DQ8 - DQ15.

For x32 DQS0 and DQS0# correspond to the data on DQ0 - DQ7, DQS1 and

DQS1# to the data on DQ8 - DQ15, DQS2 and DQS2# to the data on DQ16 - DQ23,

DQS3 and DQS3# to the data on DQ24 - DQ31.

DM0-DM1

(x16)

DM0 - DM3

(x32)

Input

Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the

input mask signal for write data. Input data is masked when DM is sampled HIGH

coincident with that input data during a Write access. DM is sampled on both edges of

DQS. Although DM is for input only, the DM loading shall match the DQ and DQS (or

DQS#).

DM0 is the input data mask signal for the data on DQ0-7.

For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.

For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is

the input data mask signal for the data on DQ24-31.

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