IS43LD16640C datasheet(84/142 Pages) ISSI

84 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

Input Clock Frequency Changes and Stop Events

LPDDR2 support Clock frequency changes and clock stop under the conditions detailed in this

section

Input Clock Frequency Changes and Clock Stop with CKE LOW

During CKE LOW, Mobile LPDDR2 devices support input clock frequency changes and clock stop

under the following conditions:

• Refresh requirements are met

• Only REFab or REFpb commands can be in process

• Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency

• Related timing conditions,tRCD and tRP, have been met prior to changing the frequency

• The initial clock frequency must be maintained for a minimum of two clock cycles after CKE goes

LOW

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to CKE going

HIGH

For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may

be required to set the WR, RL, etc. These settings may require adjustment to meet minimum timing

requirements at the target clock frequency.

For clock stop, CK is held LOW and CK# is held HIGH.

NO OPERATION Command

The NO OPERATION (NOP) command prevents the device from registering any unwanted com-

mands issued between operations. A NOP command can only be issued at clock cycle N when the

CKE level is constant for clock cycle N-1 and clock cycle N. The NOP command has two possible

encodings: CS# HIGH at the clock rising edge N; and CS# LOW with CA0, CA1, CA2 HIGH at the

clock rising edge N.

The NOP command will not terminate a previous operation that is still in process, such as a READ

burst or WRITE burst cycle

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