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IS43LD16640C bảng dữ liệu(PDF) 11 Page - Integrated Silicon Solution, Inc

tên linh kiện IS43LD16640C
Giải thích chi tiết về linh kiện  1Gb (x16, x32) Mobile LPDDR2 S4 SDRAM
PDF  142 Pages
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nhà sản xuất  ISSI [Integrated Silicon Solution, Inc]
Trang chủ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS43LD16640C bảng dữ liệu(HTML) 11 Page - Integrated Silicon Solution, Inc

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IS43/46LD16640C
IS43/46LD32320C
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. C
07/02/2021
® Long-term Support
World Class Quality
Power-Off Sequence
Use the following sequence to power off the device. Unless specified otherwise, this procedure is mandatory and
applies to S4 devices.
While powering off, CKE must be held LOW (≤ 0.2 × VDDCA); all other inputs must be between VILmin and VIHmax.
The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, DQS, and DQS# voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid
latch-up. CK, CK#, CS#, and CA input levels must be between VSSCA and VDDCA during the power-off sequence to
avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified in the DC operating condition table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off
Required Power Supply Conditions Between Tx and Tz:
• VDD1 must be greater than VDD2 - 200mV
• VDD1 must be greater than VDDCA - 200mV
• VDD1 must be greater than VDDQ - 200mV
• VREF must always be less than all other supply voltages
The voltage difference between VSS, VSSQ, and VSSCA must not exceed 100mV.
For supply and reference voltage operating conditions, see Recommended DC Operating Conditions table.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
1.At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and
all power-supply current capacity must be at zero, except for any static charge remaining in the system.
2.After Tz , the device must power off. The time between Tx and Tz must not exceed 20ms. During this period, the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5
V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device
Mode Register Definition
LPDDR2 devices contain a set of mode registers used for programming device operating parameters, reading device
information and status, and for initiating special operations such as DQ calibration, ZQ calibration, and device reset.



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