IS43LD16640C datasheet(67/142 Pages) ISSI

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IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

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MODE REGISTER READ

The MODE REGISTER READ (MRR) command is used to read configuration and status data from

SDRAM mode registers. The MRR command is initiated with CS# LOW, CA0 LOW, CA1 LOW,

CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register

is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available on the first

data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the rising edge of the clock

where MRR is issued. Subsequent data beats contain valid but undefined

content, except in the case of the DQ calibration function, where subsequent data beats contain

valid content as described in Data Calibration Pattern Description. All DQS are toggled for the

duration of the mode register READ burst. The MRR command has a burst length of four. MRR

operation (consisting of the MRR command and the corresponding data traffic) must not be inter-

rupted. The MRR command period (tMRR) is two clock cycles.

MRR Timing – RL = 3, tMRR = 2

Notes:

1. MRRs to DQ calibration registers MR32 and MR40 are described in DQ Calibration .

2. Only the NOP command is supported during tMRR.

3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid but undefined data. DQ[MAX:8]

contain valid but undefined data for the duration of the MRR burst.

4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.

5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.

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