IS43LD16640C datasheet(9/142 Pages) ISSI

9 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

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POWER-UP AND INITIALIZATION

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

The following sequence is required for Power-up and Initialization.

1. Voltage ramp up sequence is required :

A. While applying power, attempt to maintain CKE below 0.2 x VDDCA and all other inputs must be between VILmin

and VIHmax. The device outputs remain at High-Z while CKE is held LOW. The voltage ramp time tINIT0 ( Tb-Ta)

must be no greater than 20 ms from Tb which is point for all supply and reference voltage are within their defined

operating ranges , to Ta which is point for any power supply first reaches 300mV.

B. The following conditions apply for voltage ramp after Ta is reached,

− VDD1 must be greater than VDD2-200mV AND

− VDD1 and VDD2 must be greater than VDDCA-200mV AND

− VDD1 and VDD2 must be greater than VDDQ-200mV AND

− VREF must always be less than all other supply voltages

− The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV

2. Start clock and maintain stable condition.

Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100 ns, after which CKE can be asserted HIGH. The

clock must be stable at least tINIT2 = 5 × tCK prior to the first CKE LOW-to-HIGH transition (Tc). CKE, CS#, and CA

inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subse-

quent falling and rising edges).

Once the ramping of the supply voltages is complete ( Tb), CKE must be maintained LOW. DQ, DM, DQS and DQS#

voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK, CK#, CS#, and CA input

levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up

If any Mode Register Read ( MRRs ) are issued, the clock period must be within the range defined for tCKb (18ns to

100ns). Mode Register Write (MRWs) can be issued at normal clock frequencies as long as all AC timings are met.

Some AC parameters could have relaxed timings before the system is appropriately configured. While keeping CKE

HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td).

3. RESET Command

After tINIT3 is satisfied, the MRW RESET command must be issued (Td).

An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4

while keeping CKE asserted and issuing NOP commands

4. Mode Register Reads and Device Auto Initialization (DAI) Polling:

After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit commands are supported. After Te,

CKE can go LOW in alignment with power-down entry and exit specifications.

Use the MRR command to poll the DAI bit and report when device auto initialization is complete; otherwise, the con-

troller must wait a minimum of tINIT5, or until the DAI bit is set before proceeding.

As the memory output buffers are not properly configured by Te, some AC parameters must have relaxed timings

before the system is appropriately configured. After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI

complete), the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR command to MR0.

The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 or

until the DAI bit is set before proceeding

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