IS43LD16640C datasheet(33/142 Pages) ISSI

33 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

Read and Write Access Modes

After a bank is activated, a READ or WRITE command can be issued with CS# LOW, CA0 HIGH,

and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine

whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).

The LPDDR2 provide a fast column access operation .A single READ or WRITE command initiates

a burst READ or burst WRITE operation on successive clock cycles.

For LPDDR2 –S4 devices, a new burst access must not interrupt the previous 4-bit burst operation

when BL = 4.

In case of BL = 8 or BL = 16, READs can be interrupted by READs and WRITEs can be interrupted

by WRITEs, provided that the interrupt occurs on a 4-bit boundary and that tCCD is met.

Burst READ

The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 HIGH at the

rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine

the starting column address for the burst. The read latency (RL) is defined from the rising edge of

the clock on which the READ command is issued to the rising edge of the clock from which the

tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the

rising edge of the clock when the READ command is issued. The data strobe output is driven LOW

tRPRE before the first valid rising strobe edge. The first bit of the burst is synchronized with the first

rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge aligned

with the data strobe. The RL is programmed in the mode registers.

Pin input timings for the data strobe are measured relative to the crosspoint of DQS and its com-

plement, DQS#.

Data Output (Read) Timing – tDQSCK (MAX)

Data output (Read) timing (tDQSCKmax)

Notes:

1. tDQSCK can span multiple clock periods.

2. An effective burst length of 4 is shown

IS43LD16640C bảng dữ liệu(PDF) 33 Page - Integrated Silicon Solution, Inc