IS43LD16640C datasheet(25/142 Pages) ISSI

25 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

Command

Command Pins

CA Pins

Edge

CKE

CS#

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

CK( n-1)

CK( n)

NOP

Maintain PD,

SREF, DPD,

(NOP)

Enter power-

down

Exit PD, SREF,

DPD

Note:

1. All commands are defined by the current state of CS#, CA0, CA1, CA2, CA3, and CKE at

the rising edge of the clock.

2. Bank addresses (BA) determine which bank will be operated upon.

3.AP HIGH during a READ or WRITE command indicates that an auto precharge will occur

to the bank associated with the READ or WRITE command.

4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).

5. Self refresh exit and DPD exit are asynchronous.

6. VREF must be between 0 and VDDQ during self refresh and DPD operation.

7. CAxr refers to command/address bit “x” on the rising edge of clock.

8. CAxf refers to command/address bit “x” on the falling edge of clock.

9. CS# and CKE are sampled on the rising edge of the clock.

10. Per-bank refresh is only supported in devices with eight banks.

11. The least-significant column address C0 is not transmitted on the CA bus, and is inferred

to be zero

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