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IS43LD16640C bảng dữ liệu(PDF) 55 Page - Integrated Silicon Solution, Inc |
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IS43LD16640C bảng dữ liệu(HTML) 55 Page - Integrated Silicon Solution, Inc |
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55 / 142 page ![]() IS43/46LD16640C IS43/46LD32320C Integrated Silicon Solution, Inc. — www.issi.com 55 Rev. C 07/02/2021 ® Long-term Support World Class Quality REFRESH The REFRESH command is initiated with CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at the rising edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising edge of the clock. Per-bank REFRESH is only supported in devices with eight banks. A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to the bank scheduled by the bank counter in the memory device. The bank sequence for per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The bank count is synchronized between the controller and the SDRAM by resetting the bank count to zero. Synchronization can occur upon issuing a RESET command or at every exit from self refresh. Bank addressing for the per-bank REFRESH count is the same as established for the single-bank PRECHARGE com- mand. A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank REFRESH command. The REFpb command must not be issued to the device until the following conditions have been met: • tRFCab has been satisfied after the prior REFab command • tRFCpb has been satisfied after the prior REFpb command • tRP has been satisfied after the prior PRECHARGE command to that bank • tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after acti- vating a row in a different bank than the one affected by the REFpb command) The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one being refreshed can be main- tained in an active state or accessed by a READ or WRITE command. When the per-bank REFRESH cycle has completed, the affected bank will be in the idle state. After issuing REFpb, the following conditions must be met: • tRFCpb must be satisfied before issuing a REFab command • tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank • tRRD must be satisfied before issuing an ACTIVATE command to a different bank • tRFCpb must be satisfied before issuing another REFpb command |
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