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IS43LD16640C bảng dữ liệu(PDF) 45 Page - Integrated Silicon Solution, Inc |
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IS43LD16640C bảng dữ liệu(HTML) 45 Page - Integrated Silicon Solution, Inc |
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45 / 142 page ![]() IS43/46LD16640C IS43/46LD32320C Integrated Silicon Solution, Inc. — www.issi.com 45 Rev. C 07/02/2021 ® Long-term Support World Class Quality Burst READ Truncated by BST – RL = 3, BL = 16 Write Data Mask On LPDDR2 devices, one write data mask (DM) pin for each data byte (DQ) is supported, con- sistent with the implementation on LPDDR SDRAM. Each DM can mask its respective DQ for any given cycle of the burst. Data mask timings match data bit timing, but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched system timing. Data Mask Timing Notes: 1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after the rising edge of the clock where the BST command is issued. 2. BST can only be issued an even number of clock cycles after the READ command. 3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command Data Mask Timing |
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