IS43LD16640C datasheet(44/142 Pages) ISSI

44 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

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BURST TERMINATE (BST)

The BURST TERMINATE (BST) command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2

LOW, and CA3 LOW at the rising edge of the clock. A BST command can only be issued to termi-

nate an active READ or WRITE burst. Therefore, a BST command can only be issued up to and

including BL/2 - 1 clock cycles after a READ or WRITE command.

The effective burst length of a READ or WRITE command truncated by a BST command is as fol-

lows:

• Effective burst length = 2 × (number of clock cycles from the READ or WRITE command to the

BST command).

• If a READ or WRITE burst is truncated with a BST command, the effective burst length of the

truncated burst should be used for BL when calculating the minimum READ to-WRITE or WRITE-

to-READ delay.

• The BST command only affects the most recent READ or WRITE command. The BST command

truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock

where the BST command is issued. The BST command truncates an ongoing WRITE burst WL ×

tCK + tDQSS after the rising edge of the clock where the BST command is issued.

• The 4-bit prefetch architecture enables BST command assertion on even clock cycles following a

WRITE or READ command. The effective burst length of a READ or WRITE command truncated by

a BST command is thus an integer multiple of four.

Burst WRITE Truncated by BST – WL = 1, BL = 16

Burst Write truncated by BST: WL=1, BL=16

Notes:

1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock

where the BST command is issued.

2. BST can only be issued an even number of clock cycles after the WRITE command.

3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or

WRITE command.

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