IS43LD16640C datasheet(17/142 Pages) ISSI

17 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

101B:

0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW,

don’t re

-rate SDRAM AC timing

110B:

0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW,

derate SDRAM AC timing

111B:

SDRAM High temperature operating limit

exceeded

OP7

TUF (Temperature Update Flag)

Read-only

MR5_Basic Configuration 1 (MA<7:0> = 05H):

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

LPDDR2 Manufacturer ID

OP<7:0>

Manufacturer ID

Read-only

0001 1011B: ISSI

All Others : Reserved

MR6_Basic Configuration 2 (MA<7:0> = 06H):

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID1

OP<7:0>

Revision ID1

Read-only

00000000B: A-version

MR7_Basic Configuration 3 (MA<7:0> = 07H):

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID2

OP<7:0>

Revision ID2

Read-only

00000000B: A-version

B: OP <2:0> value has not changed since last read of MR4.

B: OP <2:0> value has changed since last read of MR4.

Notes:

1. A Mode Register Read from MR4 will reset OP7 to “0”.

2. OP7 is reset to “0” at power-up.

3. If OP2 equals “1”, the device temperature is greater than 85C.

4. OP7 is set to “1”, if OP2~OP0 has changed at any time since the last read of MR4.

5. LPDDR2 might not operate properly when OP<2:0> = 000B or 111B.

6. For specified operating temperature range and maximum operating temperature.

7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP,

and tRRD. The tDQSCK parameter must be derated Prevailing clock frequency specifications and related setup and

hold timings remain unchanged.

8. The recommended frequency for reading MR4 is provided in “Temperature Sensor”

9. The temperature sensor embedded in the LPDDR2 device is not an accurate reflection of the DRAM Tcase operating

temperature. Sampling of the sensor has shown up to a ±10°C variance from actual Tcase.

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