IS43LD16640C datasheet(64/142 Pages) ISSI

64 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

World Class Quality

SELF REFRESH Operation

The SELF REFRESH command can be used to retain data in the array, even if the rest of the

system is powered down. When in the self refresh mode, the device retains data without external

clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF

REFRESH command is executed by taking CKE LOW, CS# LOW, CA0 LOW, CA1 LOW, and CA2

HIGH at the rising edge of the clock.

CKE must be HIGH during the clock cycle preceding a SELF REFRESH command. A NOP com-

mand must be driven in the clock cycle following the SELF REFRESH command.

After the power-down command is registered, CKE must be held LOW to keep the device in self

refresh mode. LPDDR2-S4 devices can operate in self refresh mode in both the standard and ex-

tended temperature ranges. These devices also manage self refresh power consumption

when the operating temperature changes, resulting in the lowest possible power consumption

across the operating temperature range.

After the device has entered self refresh mode, all external signals other than CKE are“Don’t Care.”

For proper self refresh operation, power supply pins (VDD1, VDD2, VDDQ, and VDDCA) must

be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is turned off, VREFDQ

must also be turned off. Prior to exiting self refresh, both VDDQ and VREFDQ must be within their

respective minimum/maximum operating ranges . VREFDQ can be at any level between 0 and

VDDQ; VREFCA can be at any level between 0 and VDDCA during self refresh.

Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (see AC and DC

Logic Input Measurement Levels for Single-Ended Signals . After entering self refresh mode, the

device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is

internally disabled during SELF REFRESH operation to save power. The device must remain in self

refresh mode for at least tCKESR. The user can change the external clock frequency or halt the

external clock one clock after self refresh entry is registered; however, the clock must be restarted

and stable before the device can exit SELF REFRESH operation.

Exiting self refresh requires a series of commands. First, the clock must be stable prior to CKE

returning HIGH. After the self refresh exit is registered, a minimum delay, at least equal to the self

refresh exit interval (tXSR), must be satisfied before a valid command can be issued to the device.

This provides completion time for any internal refresh in progress. For proper operation, CKE must

remain HIGH throughout tXSR, except during self refresh re-entry. NOP commands must be regis-

tered on each rising clock edge during tXSR.

Using self refresh mode introduces the possibility that an internally timed refresh event could be

missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting self refresh, at least

one REFRESH command (one all-bank command or eight per-bank commands) must be issued

before issuing a subsequent SELF REFRESH command.

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