IS43LD16640C datasheet(83/142 Pages) ISSI

83 / 142 page

IS43/46LD16640C

IS43/46LD32320C

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

07/02/2021

® Long-term Support

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Deep Power-Down

Deep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0 HIGH, CA1

HIGH, and CA2 LOW at the rising edge of the clock. The NOP command must be driven in the

clock cycle following power-down entry. CKE must not go LOW while MRR or MRW operations are

in progress. CKE can go LOW while other operations such as ACTIVATE, auto precharge, PRE-

CHARGE, or REFRESH are in progress, however, deep power-down IDD specifications will not be

applied until those operations complete. The contents of the array will be lost upon entering DPD

mode.

In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal

circuitry are disabled within the device. VREFDQ can be at any level between 0 and VDDQ, and

VREFCA can be at any level between 0 and VDDCA during DPD. All power supplies (including

VREF) must be within the specified limits prior to exiting DPD (see AC and DC Operating Condi-

tions).

To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be stable. To re-

sume operation, the device must be fully reinitialized using the power-up initialization sequence.

Deep Power-Down Entry and Exit Timing

Notes:

1. The initialization sequence can start at any time after Tx + 1.

2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode Register Definition

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