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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 143 Page - Texas Instruments

tên linh kiện TMS320DM355CZCEA13
Giải thích chi tiết về linh kiện  Digital Media System-on-Chip (DMSoC)
PDF  163 Pages
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Trang chủ  http://www.ti.com
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 143 Page - Texas Instruments

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23
19
18
22
20
21
17
18
28
Stop
Start
Repeated
Start
Stop
SDA
SCL
16
TMS320DM355
www.ti.com
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
Table 5-34. Switching Characteristics for I2C Timings(1) (see Figure 5-40)
DM355
STANDARD
NO.
PARAMETER
FAST MODE
UNIT
MODE
MIN
MAX
MIN
MAX
16
tc(SCL)
Cycle time, SCL
10
2.5
ms
17
td(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START condition)
4.7
0.6
ms
Delay time, SDA low to SCL low (for a START and a repeated
18
td(SDAL-SCLL)
4
0.6
ms
START condition)
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
ms
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
ms
21
td(SDAV-SCLH)
Delay time, SDA valid to SCL high
250
100
ns
22
tv(SCLL-SDAV)
Valid time, SDA valid after SCL low (For I2C devices)
0
0
0.9
ms
23
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
ms
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
4
0.6
ms
29
Cp
Capacitance for each I2C pin
10
10
pF
(1)
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
CAUTION
The DM355 I
2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer
defined in the I
2C specification. Series resistors may be necessary to reduce noise at
the system level.
Figure 5-40. I2C Transmit Timings
Copyright © 2007–2010, Texas Instruments Incorporated
DM355 Peripheral Information and Electrical Specifications
143
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Product Folder Link(s): TMS320DM355



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