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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 146 Page - Texas Instruments

tên linh kiện TMS320DM355CZCEA13
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 146 Page - Texas Instruments

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TMS320DM355
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
www.ti.com
Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1) (2)
(see Figure 5-41)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
38.5 or 2P(3) (4)
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
ns
(5)
17
td(CLKS-CLKRX)
Delay time, CLKS high to internal CLKR/X
CLKR/X int
1
24
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C - 1(6)
C + 1(6)
ns
CLKR int
3
25
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
ns
CLKR ext
3
25
CLKX int
-4
8
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
CLKX ext
3
25
CLKX int
12
ns
tdis(CKXH-
Disable time, DX high impedance following last data
12
DXHZ)
bit from CLKX high
CLKX ext
12
ns
CLKX int
-5
12
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
3
25
ns
Delay time, FSX high to DX valid
FSX int
14
14
td(FXH-DXV)
ONLY applies when in data
ns
FSX ext
25
delay 0 (XDATDLY = 00b) mode
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2)
Minimum delay times also represent minimum output hold times.
(3)
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4)
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(5)
Use which ever value is greater.
(6)
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1 (see Section 3.5 ) )
S = sample rate generator input clock = CLKS if CLKSM = 0
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit (see footnote (3) above).
146
DM355 Peripheral Information and Electrical Specifications
Copyright © 2007–2010, Texas Instruments Incorporated
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