TMS320DM355CZCEA13 datasheet(90/163 Pages) TI1

90 / 163 page

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

www.ti.com

–

Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while

loading UBL)

–

Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)

–

Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements

≤ 4 bits per 512 bytes are

supported)

–

Supports NAND flash that requires chip select to stay low during the tR read time

Notes:

–

See Section 3.12.2 for a full explanation of the differences between Standard Mode and

Compatibility Mode.

–

The GIO000 pin must be held high during NAND boot for the boot process to fuction properly.

•

ARM ROM Boot - MMC/SD Mode

–

No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from

MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software.

–

Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported)

–

Support for descriptor error detection and retry (up to 24 times) when loading UBL

–

Support for up to 30KB UBL (32KB - ~2KB for RBL stack)

•

ARM ROM Boot - UART mode

–

No support for a full firmware boot. Instead, loads a second stage User Boot Loader (UBL) via

UART to ARM internal RAM (AIM) and transfers control to the user software.

–

Support for up to 30KB UBL (32KB - ~2KB for RBL stack)

The general boot sequence is shown in Figure 3-6. For more information, refer to TMS320DM35x Digital

Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3).

Detailed Device Description

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Product Folder Link(s): TMS320DM355

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