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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 53 Page - Texas Instruments

tên linh kiện TMS320DM355CZCEA13
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 53 Page - Texas Instruments

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TMS320DM355
www.ti.com
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
Table 2-23. DM355 Pin Descriptions (continued)
Name
BGA
Type Group
Power
PU
Reset
Description(4)
Mux Control
ID
(1)
Supply(2)
PD(3)
State
ASP1_DX
C18
I/O
ASP1
VDD
in
ASP1: Transmit Data
ASP1_CLKX
D19
I/O
ASP1
VDD
in
ASP1: Transmit Clock
ASP1_FSX
E16
I/O
ASP1
VDD
in
ASP1: Transmit Frame Sync
ASP1_DR
C19
I/O
ASP1
VDD
in
ASP1: Receive Data
ASP1_CLKR
D18
I/O
ASP1
VDD
in
ASP1: Receive Clock
ASP1_FSR
E17
I/O
ASP1
VDD
in
ASP1: Receive Frame Synch
ASP1_CLKS
D17
I
ASP1
VDD
in
ASP1: Master Clock
RESET
D11
I
VDD
PU
in
Global Chip Reset (active low)
MXI1
A9
I
Clocks
VDD
in
Crystal input for system oscillator (24 MHz)
MXO1
B9
O
Clocks
VDD
out
Output for system oscillator (24 MHz)
MXI2
R1
I
Clocks
VDD
in
Crystal input for video oscillator (27 MHz).
This crystal is not required
VDD
MXO2
T1
O
Clocks
VDD
out
Output for video oscillator (27 MHz). This
crystal is not required.
VDD
TCK
E10
I
EMUL
VDD
PU
in
JTAG test clock input
ATIO
N
TDI
D9
I
EMUL
VDD
PU
in
JTAG test data input
ATIO
N
TDO
E9
O
EMUL
VDD
out L
JTAG test data output
ATIO
N
TMS
D8
I
EMUL
VDD
PU
in
JTAG test mode select
ATIO
N
TRST
C9
I
EMUL
VDD
PD
in
JTAG test logic reset (active low)
ATIO
N
RTCK
E11
O
EMUL
VDD
out L
JTAG test clock output
ATIO
N
EMU0
E8
I/O
EMUL
VDD
PU
in
JTAG emulation 0 I/O
ATIO
VDD
N
VDD
EMU1
E7
I/O
EMUL
VDD
PU
in
JTAG emulation 1 I/O
ATIO
EMU[1:0] = 00 - Force Debug Scan chain
N
(ARM and ARM ETB TAPs connected)
EMU[1:0] = 11 - Normal Scan chain (ICEpick
only)
RSV01
J1
A
Reserved. This signal should be left as a No
I/O/Z
Connect or connected to VSS.
RSV02
K1
A
Reserved. This signal should be left as a No
I/O/Z
Connect or connected to VSS.
RSV03
L1
A
Reserved. This signal should be left as a No
I/O/Z
Connect or connected to VSS.
RSV04
M1
A
Reserved. This signal should be left as a No
I/O/Z
Connect or connected to VSS.
RSV05
N2
A
Reserved. This signal should be connected
I/O/Z
to VSS.
Copyright © 2007–2010, Texas Instruments Incorporated
Device Overview
53
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Product Folder Link(s): TMS320DM355



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