TMS320DM355CZCEA13 datasheet(46/163 Pages) TI1

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TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

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Table 2-23. DM355 Pin Descriptions (continued)

Name

BGA

Type Group

Power

Reset

Description(4)

Mux Control

(1)

Supply(2)

PD(3)

State

EM_A09 /

P17

I/O

AEMI

VDD

in L

Async EMIF: Address Bus bit[09]

PINMUX2[0].EM_A1

GIO063 /

F /

3_3,

AECFG[1]

GIO /

syste

GIO: GIO[063]

default set by

AECFG[0]

System: AECFG[3:0] sampled at

Power-on-Reset to set AEMIF Configuration

AECFG[2:1] sets default for

PinMux2.EM_BA0: AEMIF EM_BA0

Definition (00: EM_BA0, 01: EM_A14,

10:GIO[054], 11:rsvd)

EM_A08 /

T19

I/O

AEMI

VDD

in H

Async EMIF: Address Bus bit[08]

PINMUX2[0].EM_A1

GIO062 /

F /

3_3,

AECFG[0]

GIO /

syste

GIO: GIO[062]

default set by

AECFG[0]

AECFG[0] sets default for

- PinMux2.EM_A0_BA1: AEMIF Address

Width (OneNAND or NAND)

- PinMux2.EM_A13_3: AEMIF Address

Width (OneNAND or NAND)

(0:AEMIF address bits, 1:GIO[67:57])

EM_A07 /

P16

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[07]

PINMUX2[0].EM_A1

GIO061

F /

3_3,

GIO

GIO: GIO[061] - Used to drive boot status

default set by

LED signal (active low) in ROM boot modes.

AECFG[0]

EM_A06 /

P18

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[06]

PINMUX2[0].EM_A1

GIO060

F /

3_3,

GIO

GIO: GIO[060]

default set by

AECFG[0]

EM_A05 /

R19

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[05]

PINMUX2[0].EM_A1

GIO059

F /

3_3,

GIO

GIO: GIO[059]

default set by

AECFG[0]

EM_A04 /

P15

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[04]

PINMUX2[0].EM_A1

GIO058

F /

3_3,

GIO

GIO: GIO[058]

default set by

AECFG[0]

EM_A03 /

N18

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[03]

PINMUX2[0].EM_A1

GIO057

F /

3_3,

GIO

GIO: GIO[057]

default set by

AECFG[0]

EM_A02

N15

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[02]

NAND/SM/xD: CLE - Command Latch

Enable output

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