TMS320DM355CZCEA13 datasheet(17/163 Pages) TI1

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TMS320DM355

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SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Table 2-5. CCD Controller/Video Input Terminal Functions (continued)

TERMINAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Standard CCD/CMOS input: Raw[05]

•

YCC 16-bit: Time multiplexed between chroma: Y[05]

YIN5/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO091

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]

GIO: GIO[091]

Standard CCD/CMOS input: Raw[04]

•

YCC 16-bit: Time multiplexed between chroma: Y[04]

YIN4/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO090

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]

GIO: GIO[090]

Standard CCD/CMOS input: Raw[03]

•

YCC 16-bit: Time multiplexed between chroma: Y[03]

YIN3/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO089

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]

GIO: GIO[089]

Standard CCD/CMOS input: Raw[02]

•

YCC 16-bit: Time multiplexed between chroma: Y[02]

YIN2/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO088

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]

GIO: GIO[088]

Standard CCD/CMOS input: Raw[01]

•

YCC 16-bit: Time multiplexed between chroma: Y[01]

YIN1/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO087

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]

GIO: GIO[087]

Standard CCD/CMOS input: Raw[00]

•

YCC 16-bit: Time multiplexed between chroma: Y[00]

YIN0/

I/O/Z

•

YCC 8-bit (which allows for two simultaneous decoder inputs), it is time

GIO086

VDD_VIN

multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]

GIO: GIO[086]

Horizontal synchronization signal that can be either an input (slave mode) or an

CAM_HD/

I/O/Z

output (master mode). Tells the CCDC when a new line starts.

GIO085

VDD_VIN

GIO: GIO[085]

Vertical synchronization signal that can be either an input (slave mode) or an output

CAM_VD

I/O/Z

(master mode). Tells the CCDC when a new frame starts.

GIO084

VDD_VIN

GIO: GIO[084]

Write enable input signal is used by external device (AFE/TG) to gate the DDR

output of the CCDC module. Alternately, the field identification input signal is used

CAM_WEN

by external device (AFE/TG) to indicate which of two frames is input to the CCDC

_FIELD\

I/O/Z

VDD_VIN

module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in

GIO083

hardware.

GIO: GIO[083]

PCLK/

Pixel clock input (strobe for lines C17 through Y10)

I/O/Z

GIO082

VDD_VIN

GIO: GIO[0082]

2.5

Image Data Output - Video Processing Back End (VPBE)

The Video Encoder/Digital LCD interface module in the video processing back end has an external signal

interface for digital image data output as described in Table 2-7 and Table 2-8.

The digital image data output signals support multiple functions / interfaces, depending on the display

mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565

signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).

Device Overview

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