TMS320DM355CZCEA13 datasheet(64/163 Pages) TI1

64 / 163 page

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write

misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for

cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a

four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

3.2.4

Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt

Vector table. ARM internal ROM boot options include—NAND (with SPI EEPROM Boot option), SPI,

UART and MMC/SD. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled

memory interface that provides for separate instruction and data bus connections. Since the ARM TCM

does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both

data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the

RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA

support for direct accesses to the ARM internal memory from a non-ARM master. Because of the

time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are

treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the

instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the

instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,

as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB

each, which allows simultaneous instruction and data accesses to be accomplished if the code and data

are in separate banks.

3.2.5

Advanced High-performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus

and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB

by the configuration bus and the external memories bus.

3.2.6

Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an

Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM355 also includes the Embedded

Trace Buffer (ETB). The ETM consists of two parts:

•

Trace Port provides real-time trace capability for the ARM9.

•

Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The DM355 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The

ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace

data.

3.3

Memory Mapping

The ARM memory map is shown in Table 2-2 and Table 2-3. This section describes the memories and

interfaces within the ARM's memory map.

3.3.1

ARM Internal Memories

The ARM has access to the following ARM internal memories:

•

32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow

simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data

(D-TCM) to the different memory regions.

•

8KB ARM Internal ROM

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