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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 67 Page - Texas Instruments

tên linh kiện TMS320DM355CZCEA13
Giải thích chi tiết về linh kiện  Digital Media System-on-Chip (DMSoC)
PDF  163 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 67 Page - Texas Instruments

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TMS320DM355
www.ti.com
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
3.5
Device Clocking
3.5.1
Overview
The DM355 requires one primary reference clock . The reference clock frequency may be generated
either by crystal input or by external oscillator. The reference clock is the clock at the pins named
MXI1/MXO1. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1
generates the clocks required by the ARM, MPEG4 and JPEG coprocessor, VPBE, VPSS, and
peripherals. PLL2 generates the clock required by the DDR PHY. A block diagram of DM355's clocking
architecture is shown in Figure 3-2. The PLLs are described further in Section 3.6.
Copyright © 2007–2010, Texas Instruments Incorporated
Detailed Device Description
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