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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 69 Page - Texas Instruments |
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 69 Page - Texas Instruments |
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69 / 163 page  TMS320DM355 www.ti.com SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010 3.5.2 Supported Clocking Configurations for DM355-135 This section describes the only supported device clocking configurations for DM355-135. The DM355 supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. 3.5.2.1 Supported Clocking Configurations for DM355-135 (24 MHz reference) 3.5.2.1.1 DM355-135 PLL1 (24 MHz reference) All supported clocking configurations for DM355-135 PLL1 with 24 MHz reference clock are shown in Table 3-2. Table 3-2. PLL1 Supported Clocking Configurations for DM355-135 (24 MHz reference) PREDIV PLLM POSTDIV PLL1 ARM / Peripherals VENC VPSS VCO MPEG4 and JPEG Coprocessor (/8 fixed) (m programmable) (/2 or /1 (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or /2 (MHz) programmable) programmable) bypass bypass bypass bypass 2 12 4 6 10 2.4 4 6 8 180 2 270 2 135 4 67.5 10 27 2 135 8 162 2 243 2 121.5 4 60.75 9 27 2 121.5 8 144 2 216 2 108 4 54 8 27 2 108 8 126 2 189 2 94.5 4 47.25 7 27 2 94.5 8 108 2 162 2 81 4 40.5 6 27 2 81 3.5.2.1.2 DM355-135 PLL2 (24 MHz reference) All supported clocking configurations for DM355-135 PLL2 with 24 MHz reference clock are shown in Table 3-3. Table 3-3. PLL2 Supported Clocking Configurations for DM355-135 (24 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) (m programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 1 24 12 12 133 1 266 1 266 133 12 100 1 200 1 200 100 15 100 1 160 1 160 80 Copyright © 2007–2010, Texas Instruments Incorporated Detailed Device Description 69 Submit Documentation Feedback Product Folder Link(s): TMS320DM355 |
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