TMS320DM355CZCEA13 datasheet(47/163 Pages) TI1

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TMS320DM355

www.ti.com

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Table 2-23. DM355 Pin Descriptions (continued)

Name

BGA

Type Group

Power

Reset

Description(4)

Mux Control

(1)

Supply(2)

PD(3)

State

EM_A01

N17

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[01]

NAND/SM/xD: ALE - Address Latch Enable

output

EM_A00 /

M16

I/O

AEMI

VDD

out L

Async EMIF: Address Bus bit[00] Note that

PINMUX2[1].EM_A0

GIO056

F /

the EM_A0 is always a 32-bit address

_BA1,

GIO

GIO: GIO[056]

default set by

AECFG[0]

EM_BA1 /

P19

I/O

AEMI

VDD

out H

Async EMIF: Bank Address 1 signal = 16-bit

PINMUX2[1].EM_A0

GIO055

F /

address.

_BA1,

GIO

In 16-bit mode, lowest address bit.

default set by

AECFG[0]

In 8-bit mode, second lowest address bit

GIO: GIO[055]

EM_BA0 /

N19

I/O

AEMI

VDD

out H

Async EMIF: Bank Address 0 signal = 8-bit

PINMUX2[3:2].EM_

GIO054 /

F /

address.

BA0,

EM_A14

GIO

In 8-bit mode, lowest address bit.

default set by

AECFG[2:1]

Or, can be used as an extra Address line

(bit[14] when using 16-bit memories.

GIO: GIO[054]

EM_D15 /

M18

I/O

AEMI

VDD

Async EMIF: Data Bus bit[15]

PINMUX2[4].EM_D1

GIO053

F /

5_8,

GIO

GIO: GIO[053]

default set by

AECFG[3]

EM_D14 /

M19

I/O

AEMI

VDD

Async EMIF: Data Bus bit[14]

PINMUX2[4].EM_D1

GIO052

F /

5_8,

GIO

GIO: GIO[052]

default set by

AECFG[3]

EM_D13 /

M15

I/O

AEMI

VDD

Async EMIF: Data Bus bit[13]

PINMUX2[4].EM_D1

GIO051

F /

5_8,

GIO

GIO: GIO[051]

default set by

AECFG[3]

EM_D12 /

L18

I/O

AEMI

VDD

Async EMIF: Data Bus bit[12]

PINMUX2[4].EM_D1

GIO050

F /

5_8,

GIO

GIO: GIO[050]

default set by

AECFG[3]

EM_D11 /

L17

I/O

AEMI

VDD

Async EMIF: Data Bus bit[11]

PINMUX2[4].EM_D1

GIO049

F /

5_8,

GIO

GIO: GIO[049]

default set by

AECFG[3]

EM_D10 /

L19

I/O

AEMI

VDD

Async EMIF: Data Bus bit[10]

PINMUX2[4].EM_D1

GIO048

F /

5_8,

GIO

GIO: GIO[048]

default set by

AECFG[3]

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