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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 31 Page - Texas Instruments

tên linh kiện TMS320DM355CZCEA13
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TMS320DM355
www.ti.com
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
Table 2-13. USB Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
USB operating mode identification pin
For Device mode operation only, pull up this pin to VDD with a 1.5K ohm resistor.
For Host mode operation only, pull down this pin to ground (VSS) with a 1.5K ohm
USB_ID
D5
A I/O/Z
VDDA33_USB
resistor.
If using an OTG or mini-USB connector, this pin will be set properly via the
cable/connector configuration.
When USB is not used, this signal should be connected to VSS_USB.
For host or device mode operation, tie the VBUS/USB power signal to the USB
connector.
USB_VBUS
E5
A I/O/Z
VDD
When used in OTG mode operation, tie VBUS to the external charge pump and
to the VBUS signal on the USB connector.
When the USB is not used, tie VBUS to VSS_USB.
Digital output to control external 5 V supply
USB_DRVVBUS
C5
O/Z
VDD
When USB is not used, this signal should be left as a No Connect.
USB Ground Reference
VSS_USB_REF
C8
GND
VDD
Connect directly to ground and to USB_R1 via 10K ohm, 1% resistor placed as
close to the device as possible.
Analog 3.3 V power USBPHY
VDDA33_USB
J8
PWR
VDD
When USB is not used, this signal should be connected to VSS_USB.
Common mode 3.3 V power for USB PHY (PLL)
VDDA33_USB_PLL
B6
PWR
VDD
When USB is not used, this signal should be connected to VSS_USB.
Analog 1.3 V power for USB PHY
VDDA13_USB
H7
PWR
VDD
When USB is not used, this signal should be connected to VSS_USB.
Digital 1.3 V power for USB PHY
VDDD13_USB
C6
PWR
VDD
When USB is not used, this signal should be connected to VSS_USB.
2.11 Audio Interfaces
The DM355 includes two Audio Serial Ports (ASP ports), which are backward compatible with other TI
ASP serial ports and provide I2S audio interface. One interface is multiplexed with GIO signals.
Table 2-14. ASP Terminal Functions
TERMINAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
ASP0_CL
ASP0: Receive Clock
KR/
F17
I/O/Z
VDD
GIO: GIO[026]
GIO026
ASP0_CL
ASP0: Transmit Clock
KX /
F18
I/O/Z
VDD
GIO: GIO[029]
GIO029
ASP0_DR
ASP0: Receive Data
/
E18
I/O/Z
VDD
GIO: GIO[027]
GIO027
ASP0_DX
ASP0: Transmit Data
/
H15
I/O/Z
VDD
GIO: GIO[030]
GIO030
ASP0_FS
ASP0: Receive Frame Synch
R /
F16
I/O/Z
VDD
GIO: GIO[025]
GIO025
ASP0_FS
X /
G17
I/O/Z
VDD
ASP0: Transmit Frame SynchGIO: GIO[028]
GIO028
ASP1_CL
D18
I/O/Z
VDD
ASP1: Receive Clock
KR
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2)
Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail.
(3)
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
Ω resistor should be used.)
Copyright © 2007–2010, Texas Instruments Incorporated
Device Overview
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Product Folder Link(s): TMS320DM355



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