TMS320DM355CZCEA13 datasheet(147/163 Pages) TI1

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Bit(n-1)

(n-2)

(n-3)

Bit0

Bit(n-1)

(n-2)

(n-3)

13(A)

A. ParameterNo.13appliestothefirstdatabitonly whenXDATDLY ≠ 0.

CLKR

FSR(int)

FSR(ext)

CLKX

FSX(int)

FSX(ext)

FSX

(XDATDLY=00b)

CLKS

TMS320DM355

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SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Figure 5-41. ASP Timing

Table 5-37. ASP as SPI Timing Requirements

CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)

MASTER

NO.

PARAMETER

UNIT

MIN

MAX

M30

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

M31

th(CKXL-DRV)

Hold time, DR valid after CLKX low

Table 5-38. ASP as SPI Switching Characteristics(1) (2)

CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)

MASTER

NO.

PARAMETER

UNIT

MIN

MAX

38.5 or

M33

tc(CKX)

Cycle time, CLKX

2P(1) (3)

M24

td(CKXL-FXH)

Delay time, CLKX low to FSX high(2)

T – 2

T + 3

M25

td(FXL-CKXH)

Delay time, FSX low to CLKX high(4)

L1 – 2

L1 + 2

M26

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–2

M27

tdis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from CLKX low

L1 – 3

L1 +3

(1)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .

(2)

T = CLKX period = (1 + CLKGDV) × 2P

L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even

(3)

Use which ever value is greater.

(4)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

DM355 Peripheral Information and Electrical Specifications

147

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