TMS320DM355CZCEA13 datasheet(151/163 Pages) TI1

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Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

M59

M58

M55

M57

M56

M54

M53

CLKX

FSX

M62

TMS320DM355

www.ti.com

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Table 5-43. ASP as SPI Timing Requirements

CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)

MASTER

NO.

PARAMETER

UNIT

MIN

MAX

M58

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

M59

th(CKXL-DRV)

Hold time, DR valid after CLKX low

Table 5-44. ASP as SPI Switching Characteristics(1) (2)

CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)

MASTER

NO.

PARAMETER

UNIT

MIN

MAX

38.5 or 2P(3)

M62

tc(CKX)

Cycle time, CLKX

(3)

M53

td(CKXH-FXH)

Delay time, CLKX high to FSX high(4)

H1 – 1

H1 + 3

M54

td(FXL-CKXL)

Delay time, FSX low to CLKX low(5)

T – 2

T + 2

M55

td(CKXL-DXV)

Delay time, CLKX low to DX valid

–2

Disable time, DX high impedance following last data bit from

M56

tdis(CKXH-DXHZ)

– 3

+ 3

CLKX high

M57

td(FXL-DXV)

Delay time, FSX low to DX valid

L1 – 1

L1 + 10

(1)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .

(2)

T = CLKX period = (1 + CLKGDV) × 2P

L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even

H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even

(3)

Use which ever value is greater.

(4)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP

(5)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1

DM355 Peripheral Information and Electrical Specifications

151

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