TMS320DM355CZCEA13 datasheet(140/163 Pages) TI1

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SPI_CLK

(ClockPolarity=0)

SPI_CLK

(ClockPolarity=1)

SPI_DI

(Input)

SPI_DO

(Output)

MSBIN

DATA

LSBIN

LSBOUT

MSBOUT

DATA

SPI_EN

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

www.ti.com

SPI Master Mode Timings (Clock Phase = 1)

Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

Setup time, SPI_DI (input) valid before SPI_CLK (output)

tsu(DIV-CLKL)

Clock Polarity = 0

.5P + 3

rising edge

Setup time, SPI_DI (in put) valid before SPI_CLK (output)

tsu(DIV-CLKH)

Clock Polarity = 1

.5P + 3

falling edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) rising

th(CLKL-DIV)

Clock Polarity = 0

.5P + 3

edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) falling

th(CLKH-DIV)

Clock Polarity = 1

.5P + 3

edge

Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode

[Clock Phase = 1] (see Figure 5-38)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, SPI_CLK (output) falling edge to SPI_DO

td(CLKL-DOV)

Clock Polarity = 0

-4

(output) transition

Delay time, SPI_CLK (output) rising edge to SPI_DO

td(CLKH-DOV)

Clock Polarity = 1

-4

(output) transition

Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling

2P+.5C

td(ENL-CLKH/L)

(1)

edge

(1)

td(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance

P(2)

(2)

(1)

The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface

(SPI) User's Guide (literature number SPRUED4).

(2)

The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface

(SPI) User's Guide (literature number SPRUED4).

Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1)

140

DM355 Peripheral Information and Electrical Specifications

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