PCI9060ES datasheet(117/192 Pages) ETC

117 / 192 page

SECTION 8

PCI 9080

TIMING DIAGRAMS

©PLX Technology, Inc., 1997

Page 108

Version 1.02

J Mode Direct Slave

Timing Diagram 8-64. (J Mode) PCI 9080 Direct Slave Burst Read from Local Bus

Timing Diagram 8-65. (J Mode) PCI 9080 Direct Slave Burst Write to Local Bus, Bterm Enabled

Timing Diagram 8-66. (J Mode) PCI 9080 DMA or Direct Slave Burst Write to Local Bus, Bterm Disabled

Timing Diagram 8-67. (J Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting

Timing Diagram 8-68. (J Mode) Direct Slave Read v2.1 Spec

Timing Diagram 8-69. (J Mode) Direct Slave Read No Flush Mode (Read Ahead Mode)

Timing Diagram 8-70. (J Mode) Local Bus Read from PCI 9080 CFG Registers

Timing Diagram 8-71. (J Mode) Local Bus Write to PCI 9080 CFG Registers

J Mode Direct Master

Timing Diagram 8-72. (J Mode) Direct Master Read Access from PCI Bus (Keep PCI Bus If Read FIFO Full Mode), No PCI

Disconnects

Timing Diagram 8-73. (J Mode) Local Bus Direct Master Burst Write Access to PCI Bus, Continuous If Same Clock Rate and No PCI

Disconnects

Timing Diagram 8-74. (J Mode) Local Bus Direct Master Lock Memory Read Access from PCI Bus Followed by Write and Release

J Mode DMA

Timing Diagram 8-75. (J Mode) PCI 9080 DMA Local to PCI

Timing Diagram 8-76. (J Mode) PCI 9080 DMA PCI to Local Bus

Timing Diagram 8-77. (J Mode) DMA Read of Chaining Parameters

Timing Diagram 8-78. (J Mode) PCI 9080 Write to Local Bus BREQ Asserted

S Mode

Timing Diagram 8-79. (S Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16 Bit Local Bus

Timing Diagram 8-80. (S Mode) Local Bus Read from PCI 9080 CFG Registers

Timing Diagram 8-81. (S Mode) Local Bus Write to PCI 9080 CFG Registers

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