PCI9060ES datasheet(90/192 Pages) ETC

90 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 81

Version 1.02

4.6.7 (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register

Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register

Field

Description

Read

Write

Value after Reset

31:0

PCI Data Address Register. Indicates from where in the PCI memory space the

DMA transfers (reads or writes) start.

Yes

4.6.8 (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register

Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register

Field

Description

Read

Write

Value after Reset

31:0

Local Data Address Register. Indicates from where in the local memory space the

DMA transfers (reads or writes) start.

Yes

4.6.9 (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register

Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register

Field

Description

Read

Write

Value after Reset

22:0

DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA

operation.

Yes

31:23

Reserved.

Yes

4.6.10 (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register

Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register

Field

Description

Read

Write

Value after Reset

Descriptor Location. Value of 1 indicates PCI address space. Value of 0 indicates

Local Address Space.

Yes

End of Chain. Value of 1 indicates end of chain. Value of 0 indicates not end of

chain descriptor. (Same as Nonchaining Mode.)

Yes

Interrupt after Terminal Count. Value of 1 causes an interrupt to be generated after

the terminal count for this descriptor is reached. Value of 0 disables interrupts from

being generated.

Yes

Direction of Transfer. Value of 1 indicates transfers from local bus to PCI bus. Value

of 0 indicates transfers from PCI bus to local bus.

Yes

31:4

Next Descriptor Address. Quad word aligned (bits [3:0] = 0000).

Yes

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