PCI9060ES datasheet(77/192 Pages) ETC

77 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 68

Version 1.02

4.4.8 (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI

Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI

Field

Description

Read

Write

Value after Reset

15:0

Reserved (64 KB increments).

Yes

31:16

Specifies which local address bits to use for decoding a local to PCI bus access.

Each of the bits corresponds to a PCI address bit. Bit 31 corresponds to Address bit

31. Write a value of 1 to all bits that must be included in decode and a 0 to all

others. This range register is used for Direct Master memory, I/O, or configuration

accesses.

Yes

Note:

Range (not Range register) must be power of 2. “Range register value” is the inverse of range.

4.4.9

(DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to

PCI Memory

Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory

Field

Description

Read

Write

Value after Reset

15:0

Reserved.

Yes

31:16

Assigns a value to the bits to use for decoding a local to PCI memory access.

Yes

Note:

Local Base Address value must be multiple of Range (not the Range register).

4.4.10

(DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI

IO/CFG

Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG

Field

Description

Read

Write

Value after Reset

15:0

Reserved.

Yes

31:16

Assigns a value to the bits to use for decoding a local to PCI I/O or configuration

access. This base address is used for Direct Master I/O and configuration

accesses.

Yes

Notes: Local Base Address value must be multiple of Range (not the Range register).

Refer to bit 13 of (LOC:A8h) for I/O Remap Address option (refer to Table 4-43).

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