PCI9060ES datasheet(5/192 Pages) ETC

5 / 192 page

PCI 9080

TABLE OF CONTENTS

©PLX Technology, Inc., 1997

Page vi

Version 1.01

3.13.5

Inbound Post List FIFO ..................................................................................................................................................... 41

3.13.6

Outbound Post List FIFO .................................................................................................................................................. 41

3.13.7

Outbound Post Queue ...................................................................................................................................................... 41

3.13.8

Inbound Free Queue......................................................................................................................................................... 41

3.13.9

Outbound Free List FIFO .................................................................................................................................................. 41

3.13.10

I20 Enable Sequence .................................................................................................................................................... 42

REGISTERS ...................................................................................................................................................................43

4.1

NEW REGISTER DEFINITIONS SUMMARY .........................................................................................................43

4.1.1

Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD.................................................. 44

4.2

REGISTER ADDRESS MAPPING..........................................................................................................................50

4.2.1

PCI Configuration Registers ............................................................................................................................................. 50

4.2.2

Local Configuration Registers........................................................................................................................................... 51

4.2.3

Runtime Registers ............................................................................................................................................................ 52

4.2.4

DMA Registers.................................................................................................................................................................. 53

4.2.5

Messaging Queue Registers............................................................................................................................................. 54

4.3

PCI CONFIGURATION REGISTERS .....................................................................................................................55

4.3.1

(PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ............................................................................................ 55

4.3.2

(PCICR; PCI:04h, LOC:04h) PCI Command Register ...................................................................................................... 55

4.3.3

(PCISR; PCI:06h, LOC:06h) PCI Status Register............................................................................................................. 56

4.3.4

(PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register .................................................................................................. 56

4.3.5

(PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register....................................................................................... 57

4.3.6

(PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register ....................................................................................... 57

4.3.7

(PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register ............................................................................................. 57

4.3.8

(PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register ............................................................................................... 57

4.3.9

(PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register ........................................................................... 58

4.3.10

(PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime,

and DMA Registers........................................................................................................................................................... 58

4.3.11

(PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and

DMA Registers.................................................................................................................................................................. 59

4.3.12

(PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 ............... 59

4.3.13

(PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 .............. 60

4.3.14

(PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register ............................................................................................ 60

4.3.15

(PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register ............................................................................................ 60

4.3.16

(PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register ..................................................................................... 61

4.3.17

(PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register................................................................................ 61

4.3.18

(PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register ............................................................................................... 61

4.3.19

(PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register ............................................................................ 61

4.3.20

(PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register ................................................................................................ 61

4.3.21

(PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register ................................................................................................. 62

4.3.22

(PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register ..................................................................................................... 62

PCI9060ES bảng dữ liệu(PDF) 5 Page - List of Unclassifed Manufacturers

PCI9060ES bảng dữ liệu(HTML) 5 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL