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PCI9060ES bảng dữ liệu(PDF) 81 Page - List of Unclassifed Manufacturers

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Giải thích chi tiết về linh kiện  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
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PCI9060ES bảng dữ liệu(HTML) 81 Page - List of Unclassifed Manufacturers

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SECTION 4
PCI 9080
REGISTERS
©PLX Technology, Inc., 1997
Page 72
Version 1.02
4.5 RUNTIME REGISTERS
4.5.1 (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0
Table 4-48. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0
Field
Description
Read
Write
Value after Reset
31:0
32 Bit Mailbox Register.
Yes
Yes
0
Note:
Mailbox Register 0 is replaced by the Inbound Queue Port when the I2O feature is enabled (bit 0 in the QSR
register is set). Mailbox Register 0 is always accessible at PCI address 78h and local address C0h.
4.5.2 (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1
Table 4-49. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1
Field
Description
Read
Write
Value after Reset
31:0
32 Bit Mailbox Register.
Yes
Yes
0
Note:
Mailbox Register 1 is replaced by the Outbound Queue Port when the I2O feature is enabled (bit 0 in the QSR
register is set). Mailbox Register 1 is always accessible at PCI address 7Ch and local address C4h.
4.5.3 (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2
Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2
Field
Description
Read
Write
Value after Reset
31:0
32 Bit Mailbox Register.
Yes
Yes
0
4.5.4 (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3
Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3
Field
Description
Read
Write
Value after Reset
31:0
32 Bit Mailbox Register.
Yes
Yes
0
4.5.5 (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4
Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4
Field
Description
Read
Write
Value after Reset
31:0
32 Bit Mailbox Register.
Yes
Yes
0



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