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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PCI9060ES bảng dữ liệu(PDF) 95 Page - List of Unclassifed Manufacturers |
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PCI9060ES bảng dữ liệu(HTML) 95 Page - List of Unclassifed Manufacturers |
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95 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 86 Version 1.02 4.7.7 (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register Table 4-81. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Free Head Pointer. Local Memory Offset for Inbound Free List FIFO. This register is initialized as (0*FIFO Size) and maintained by the local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.8 (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register Table 4-82. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Free Tail Pointer. Local Memory Offset for Inbound Free List FIFO. This register is initialized as (0*FIFO Size) by the local CPU software. It is maintained by the MU hardware and is incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.9 (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register Table 4-83. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Post Head Pointer. Local Memory Offset for Inbound Post List FIFO. This register is initialized as (1*FIFO Size) by the local CPU software. It is maintained by the MU hardware and is incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.10 (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register Table 4-84. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Post Tail Pointer. Local Memory Offset for Inbound Post List FIFO. This register is initialized as (1*FIFO Size) and maintained by the local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 |
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