PCI9060ES datasheet(84/192 Pages) ETC

tên linh kiện	PCI9060ES

Giải thích chi tiết về linh kiện	12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS

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SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 75

Version 1.02

Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register (continued)

Field

Description

Read

Write

Value after Reset

Value of 0 indicates a Direct Master was the bus master during a Master or Target

abort. (Not valid until abort occurs.)

Yes

Value of 0 indicates DMA CH 0 was the bus master during a Master or Target

abort. (Not valid until abort occurs.)

Yes

Value of 0 indicates DMA CH 1 was the bus master during a Master or Target

abort. (Not valid until abort occurs.)

Yes

Value of 0 indicates a Target Abort was generated by the PCI 9080 after 256

consecutive Master retries to a Target. (Not valid until abort occurs.)

Yes

Value of 1 indicates PCI wrote data to the MailBox #0. Enabled only if

MBOXINTENB is enabled (bit 3 high).

Yes

Value of 1 indicates PCI wrote data to the MailBox #1. Enabled only if

MBOXINTENB is enabled (bit 3 high).

Yes

Value of 1 indicates PCI wrote data to the MailBox #2. Enabled only if

MBOXINTENB is enabled (bit 3 high).

Yes

Value of 1 indicates PCI wrote data to the MailBox #3. Enabled only if

MBOXINTENB is enabled (bit 3 high).

Yes

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