PCI9060ES datasheet(23/192 Pages) ETC

tên linh kiện	PCI9060ES

Giải thích chi tiết về linh kiện	12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 14

Version 1.02

Table 3-2. Short Serial EEPROM Load Registers

Serial

EEPROM

Offset

Description

Sample

Serial

EEPROM

Value

Device ID

9080

Vendor ID

10B5

Class Code

0680

Class Code, Revision

0002

Maximum Latency, Minimum Grant

0000

Interrupt Pin, Interrupt Line Routing

0100

MSW of Mailbox 0 (User Defined)

xxxx

LSW of Mailbox 0 (User Defined)

xxxx

MSW of Mailbox 1 (User Defined)

xxxx

LSW of Mailbox 1 (User Defined)

xxxx

3.3.2 Long Serial EEPROM Load

The registers listed in Table 4-39 are loaded from serial

EEPROM after reset is de-asserted if SHORT# pin is

high. The serial EEPROM is organized in words (16 bit).

PCI 9080 first loads MSW (Most Significant Word; bits

[31:16]), starting from the most significant bit (bit 31).

PCI 9080 then loads LSW (Least Significant Word; bits

[15:0]), starting again from the most significant bit

(bit 15). Therefore, PCI 9080 will load Device ID, Vendor

ID, class code, and so forth.

The serial EEPROM value can be entered into a DATA

I/O programmer in the order shown below. The values

shown are examples and must be modified for each

particular application. The 34 16-bit words listed in the

table are stored sequentially in the serial EEPROM.

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