PCI9060ES datasheet(97/192 Pages) ETC

97 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 88

Version 1.02

4.7.15 (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register

Table 4-89. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register

Field

Description

Read

Write

Value after Reset

0I20 Decode Enable. When this bit is set, Mailbox registers 0 and 1 are replaced by

the Inbound and Outbound Queue Port Registers and redefines Space 1 as PCI

Base Address 0 to be accessed by PCIBAR0. Former Space 1 registers F0, F4,

and F8 should be programmed to configure their shared I20 memory space, defined

as PCI Base Address 0.

Yes

Queue Local Space Select. When this bit is set to 0, use Local Address Space 0

bus region descriptor for queue accesses. When this bit is set to 1, use Local

Address Space 1 bus region descriptor for queue accesses.

Yes

Outbound Post List FIFO Prefetch Enable. When this bit is set, prefetching occurs

from the Outbound Post List FIFO if not empty.

Yes

Inbound Free List FIFO Prefetch Enable. When this bit is set, prefetching occurs

from the Inbound Free List FIFO if not empty.

Yes

Inbound Post List FIFO Interrupt Mask. Interrupt is masked when bit is set.

Yes

Inbound Post List FIFO Interrupt. This bit is set when the Inbound Post List FIFO

is not empty. This bit is not affected by the Interrupt Mask bit.

Yes

Outbound Free List FIFO Overflow Interrupt Mask. Interrupt is masked when bit

is set.

Yes

Outbound Free List FIFO Overflow Interrupt. This bit is set when the Outbound Free

List FIFO becomes full. A local LSERR (NMI) interrupt is generated if enabled in the

Interrupt Control/Status Register. Writing 1 clears the interrupt.

Yes

Yes/Clr

31:8

Unused.

Yes

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