PCI9060ES datasheet(78/192 Pages) ETC

78 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 69

Version 1.02

4.4.11 (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to

PCI Memory

Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory

Field

Description

Read

Write

Value after Reset

Direct Master Memory Access Enable. Value of 1 enables decode of Direct Master

Memory accesses. Value of 0 disables decode of Direct Master Memory accesses.

Yes

Direct Master I/O Access Enable. Value of 1 enables decode of Direct Master I/O

accesses. Value of 0 disables decode of Direct Master I/O accesses.

Yes

LLOCK# Input Enable. Value of 1 enables LLOCK# input, enabling PCI-locked

sequences. Value of 0 disables LLOCK# input.

Yes

12, 3

Direct Master Read Prefetch Size control. Values:

00 = PCI 9080 continues to prefetch read data from the PCI bus until Direct Master

access is finished. This may result in an additional four unneeded Lwords being

prefetched from the PCI bus.

01 = Prefetch up to four Lwords from the PCI bus

10 = Prefetch up to eight Lwords from the PCI bus

11 = Prefetch up to 16 Lwords from the PCI bus

If PCI memory prefetch is not wanted, performs a Direct Master single cycle.

The direct master burst reads must not exceed the programmed limit.

Yes

Direct Master PCI Read Mode. Value of 0 indicates PCI 9080 should release the

PCI bus when the read FIFO becomes full. Value of 1 indicates PCI 9080 should

keep the PCI bus and de-assert IRDY when the read FIFO becomes full.

Yes

10, 8:5

Programmable Almost Full Flag. When the number of entries in the 32 word direct

master write FIFO exceeds this value, the output pin DMPAF# is asserted low.

Yes

000

Write and Invalidate Mode. When set to 1, PCI 9080 waits for 8 or 16 Lwords to be

written from the local bus before starting PCI access. When set, all local Direct

Master to PCI write accesses must be 8 or 16 Lword bursts.

Use in conjunction with (PCI:04h)(LOC:04h) (refer to Table 4-11[4] and Section

3.6.1.9.2, “Direct Master Write and Invalidate”).

Yes

Direct Master Prefetch Limit. If set to 1, don’t prefetch past 4K (4098 bytes)

boundaries.

Yes

I/O Remap Select. When set to 1, forces PCI address bits [31:16] to all zeros.

When set to 0, uses bits [31:16] of this register as PCI address bits [31:16].

Yes

15:14

Direct Master Write Delay. This register is used to delay the PCI bus request after

direct master burst write cycle has started. Values:

00 = No delay; start the cycle immediately

01 = Delay 4 PCI clocks

10 = Delay 8 PCI clocks

11 = Delay 16 PCI clocks

Yes

31:16

Remap of Local to PCI Space into a PCI Address Space. The bits in this register

remap (replace) the local address bits used in decode as the PCI address bits. This

PCI Remap address is used for Direct Master memory and I/O accesses.

Yes

Note:

Remap Address value must be multiple of Range (not the Range register).

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