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PCI9060ES bảng dữ liệu(PDF) 71 Page - List of Unclassifed Manufacturers

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Giải thích chi tiết về linh kiện  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
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PCI9060ES bảng dữ liệu(HTML) 71 Page - List of Unclassifed Manufacturers

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SECTION 4
PCI 9080
REGISTERS
©PLX Technology, Inc., 1997
Page 62
Version 1.02
4.3.21 (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register
Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register
Field
Description
Read
Write
Value after Reset
7:0
Interrupt Pin Register. Indicates which interrupt pin the device uses. The following
values are decoded:
0 = No Interrupt Pin
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
Note:
PCI 9080 supports only one PCI interrupt pin (INTA#).
Yes
Local/
Serial
EEPROM
1
4.3.22 (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register
Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register
Field
Description
Read
Write
Value after Reset
7:0
Min_Gnt. Specifies how long a burst period the device needs, assuming a clock
rate of 33 MHz. Value is multiple of 1/4 µsec increments.
Yes
Local/
Serial
EEPROM
0
4.3.23 (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register
Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register
Field
Description
Read
Write
Value after Reset
7:0
Max_Lat. Specifies how often the device must gain access to the PCI bus. Value
is multiple of 1/4 µsec increments.
Yes
Local/
Serial
EEPROM
0



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