PCI9060ES datasheet(75/192 Pages) ETC

75 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 66

Version 1.02

4.4.5 (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register

Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register

Field

Description

Read

Write

Value after Reset

10:0

Reserved.

Yes

31:11

Specifies which PCI address bits to use for decoding a PCI to local bus expansion

ROM. Each of the bits corresponds to a PCI address bit. Bit 31 corresponds to

Address bit 31. Write a value of 1 to all bits to be included in decode and a 0 to all

others (used in conjunction with PCI Configuration register 30h). Default is 64 KB.

Yes

FFFF00h

Note:

Range (not Range register) must be power of 2. “Range register value” is the inverse of range.

4.4.6

(EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register

and BREQo Control

Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo

Control

Field

Description

Read

Write

Value after Reset

3:0

Direct Slave BREQo (Backoff Request Out) Delay Clocks. Number of local bus

clocks in which a Direct Slave HOLD request is pending and a Local Direct Master

access is in progress and not being granted the bus (LHOLDA) before asserting

BREQo. Once asserted, BREQo remains asserted until the PCI 9080 receives

LHOLDA (LSB = 8 or 64 clocks).

Yes

Local Bus BREQo Enable. Value of 1 enables PCI 9080 to assert the BREQo

output.

Yes

BREQo Timer-Resolution. Value of 1 changes the LSB of the BREQo timer from 8

to 64 clocks.

Yes

10:6

Reserved.

Yes

31:11

Remap of PCI Expansion ROM Space into a Local Address Space. The bits in this

bits.

Yes

Note:

Remap Address value must be multiple of Range (not the Range register).

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