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PCI9060ES bảng dữ liệu(PDF) 57 Page - List of Unclassifed Manufacturers |
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PCI9060ES bảng dữ liệu(HTML) 57 Page - List of Unclassifed Manufacturers |
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57 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 48 Version 1.02 Table 4-4. Register Differences between PCI 9080 and PCI 9060SD Register PCI/Local Offset Bits Description PCIIDR 00/00 31:16 Default changed from PCI 906D to PCI 9080 PCISR 06/06 6 User definable bit added PCIBAR0 10/10 8:6 Register Bank size changed from 128 to 256 PCIBAR1 14/14 8:6 Register Bank size changed from 128 to 256 PCISVID 2C/2C 15:0 Subsystem Vendor ID Register PCISID 2E/2E 15:0 Subsystem ID Register 31:0 Mode/Arbitration Register now accessible from PCI bus 23 PCI Request Mode MARBR 08, AC/88, 12C 28 PCI Read/No Flush Mode 1 Direct Master Big Endian Mode BIGEND 0C/8C 7 DMA Channel 0 Big Endian Mode 3:0 Direct Slave BREQo Delay Clocks 4 Local Bus BREQo Enable EROMBA 14/94 5 BREQo Timer Resolution control 1:0 Local bus width now programmable in S mode 15 Single Read Access Mode removed LBRD0 18/98 17:16 Local bus width now programmable in S mode DMRR 1C/9C 31:16 Local Range Register for Direct Master to PCI DMLBAM 20/A0 31:0 Local Bus Base Address Register for Direct Master to PCI Memory DMLBAI 24/A4 31:0 Local Bus Base Address Register for Direct Master to PCI IO/CFG DMPBAM 28/A8 31:0 PCI Base Address (Remap) Register for Direct Master to PCI Memory LAS1RR F0/170 31:0 Local Address Space 1 Range Register was at 30/B0 in PCI 9060SD LAS1BA F4/174 31:0 Local Address Space 1 Local Base Address Register (Remap) was at 34/B4 in PCI 9060SD LBRD1 F8/178 31:0 Local Address Space 1 Bus Region Descriptor Register was at 38/B8 in PCI 9060SD LBRD1 F8/178 15 Single Read Access Mode removed MBOX0 40,78/C0 31:0 MBOX0 moved to PCI address 78 when Messaging Queue is enabled MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI address 7C when Messaging Queue is enabled MBOX4 50/D0 31:0 MBOX4 added MBOX5 54/D4 31:0 MBOX5 added MBOX6 58/D8 31:0 MBOX6 added MBOX7 5C/DC 31:0 MBOX7 added 18 DMA Channel 0 interrupt enable 21 DMA Channel 0 interrupt active 24 Direct Master active during abort INTCSR 68/E8 25 DMA Channel 0 active during abort PCIHREV 74/F4 7:0 PCI Permanent Revision ID Register |
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