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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PCI9060ES bảng dữ liệu(PDF) 96 Page - List of Unclassifed Manufacturers |
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PCI9060ES bảng dữ liệu(HTML) 96 Page - List of Unclassifed Manufacturers |
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96 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 87 Version 1.02 4.7.11 (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register Table 4-85. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Free Head Pointer. Local Memory Offset for Outbound Free List FIFO. This register is initialized as (3*FIFO Size) by the local CPU software and is maintained by the MU hardware and is incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.12 (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register Table 4-86. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Free Tail Pointer. Local Memory Offset for Outbound Free List FIFO. This register is initialized as (3*FIFO Size) and maintained by the local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.13 (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register Table 4-87. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Post Head Pointer. Local Memory Offset for Outbound Post List FIFO. This register is initialized as (2*FIFO Size) and maintained by the local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 4.7.14 (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register Table 4-88. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register Field Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Post Tail Pointer. Local Memory Offset for Outbound Post List FIFO. This register is initialized as (2*FIFO Size) and maintained by the MU hardware and is incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 |
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