PCI9060ES datasheet(10/192 Pages) ETC

10 / 192 page

PCI 9080

PCI I/O ACCELERATOR

JULY 24, 1997

I2O COMPATIBLE PCI BUS MASTER INTERFACE CHIP

VERSION 1.02

FOR ADAPTERS AND EMBEDDED SYSTEMS

©PLX Technology, Inc., 1997

Page 1

Version 1.02

FEATURES

•

PCI Version 2.1 compliant Bus Master Interface chip

for adapters and embedded systems

•

I2O Compatible Messaging Unit

•

3.3 or 5 Volt PCI signaling, 5 volt core, low-power

CMOS in 208-pin PQFP

•

Two independent DMA channels for local bus

memory to/from PCI host bus data transfers

•

Eight programmable FIFOs for zero wait state burst

operation

•

PCI

Local data transfers up to 132 MB/sec

•

Programmable local bus supports nonmultiplexed

32-bit address/data, multiplexed 32 or 16 bit, and

slave accesses of 32, 16, or 8 bit local bus devices

•

Local bus runs asynchronously to the PCI bus

•

Eight 32 bit mailbox and two 32 bit doorbell registers

•

Performs Big Endian/Little Endian conversion

•

Upward compatibility with PCI 9060/9060ES/9060SD

1. GENERAL DESCRIPTION

PCI 9080 provides a compact, high performance PCI

bus master interface for adapter boards and embedded

systems. The programmable local bus of the chip can be

configured

directly

connect

wide

variety

processors, controllers and memory subsystems.

PCI 9080 contains an Intelligent I/O (I2O) messaging unit

that allows high performance and compatible software

implementations of the I2O bus protocol specification.

Users of the PCI 9060, 9060ES and 9060SD chips may

upgrade their products to support I2O, 3.3 Volts and

other new features with little or no change to existing

hardware and software.

PCI 9080 provides eight programmable FIFOs. Each

operating

mode—slave,

direct,

master,

and

DMA

channel—have dedicated, independent read and write

FIFOs. PCI 9080 also allows a local processor to

configure other PCI devices in the system.

Figure 1-1. Typical Adapter or Block Diagram

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