PCI9060ES datasheet(19/192 Pages) ETC

19 / 192 page

SECTION 2

PCI 9080

BUS OPERATION

©PLX Technology, Inc., 1997

Page 10

Version 1.02

Table 2-11. Upper Lword Lane Transfer

Burst Order

Byte Lane

Byte 0 appears on Local Data [31:24]

Byte 1 appears on Local Data [23:16]

Byte 2 appears on Local Data [15:8]

First Transfer

Byte 3 appears on Local Data [7:0]

Figure 2-2. Big/Little Endian—32 Bit Local Bus

2.2.3.8.2 16 Bit Local Bus—Big Endian Mode

For a 16 bit local bus, PCI 9080 can be programmed to

use the upper or lower word lane. Byte lanes and burst

order are listed in Table 2-12 and Table 2-13 and

illustrated in Figure 2-3.

Table 2-12. Upper Word Lane Transfer

Burst Order

Byte Lane

Byte 0 appears on Local Data [31:24]

First Transfer

Byte 1 appears on Local Data [23:16]

Byte 2 appears on Local Data [31:24]

Second Transfer

Byte 3 appears on Local Data [23:16]

Table 2-13. Lower Word Lane Transfer

Burst Order

Byte Lane

Byte 0 appears on Local Data [15:8]

First Transfer

Byte 1 appears on Local Data [7:0]

Byte 2 appears on Local Data [15:8]

Second Transfer

Byte 3 appears on Local Data [7:0]

Figure 2-3. Big/Little Endian—16 Bit Local Bus

2.2.3.8.3 8 Bit Local Bus—Big Endian Mode

For an 8 bit local bus, PCI 9080 can be programmed to

use the upper or lower byte lane. Byte lanes and burst

order are listed in Table 2-14 and Table 2-15 and

illustrated in Figure 2-4.

Table 2-14. Upper Byte Lane Transfer

Burst Order

Byte Lane

First transfer

Byte 0 appears on Local Data [31:24]

Second transfer

Byte 1 appears on Local Data [31:24]

Third transfer

Byte 2 appears on Local Data [31:24]

Fourth transfer

Byte 3 appears on Local Data [31:24]

Table 2-15. Lower Byte Lane Transfer

Burst Order

Byte Lane

First Transfer

Byte 0 appears on Local Data [7:0]

Second Transfer

Byte 1 appears on Local Data [7:0]

Third Transfer

Byte 2 appears on Local Data [7:0]

Fourth Transfer

Byte 3 appears on Local Data [7:0]

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