PCI9060ES datasheet(91/192 Pages) ETC

91 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 82

Version 1.02

4.6.11 (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register

Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register

Field

Description

Read

Write

Value after Reset

Channel 0 Enable. Value of 1 enables channel to transfer data. Value of 0 disables

channel from starting a DMA transfer and if in the process of transferring data

suspend transfer (pause).

Yes

Channel 0 Start. Writing 1 to this bit causes channel to start transferring data

if the channel is enabled.

Yes/Set

Channel 0 Abort. Writing 1 to this bit causes channel to abort the current transfer.

Channel enable bit must be cleared. Channel complete bit is set when the abort is

complete.

Yes/Set

Clear Interrupt. Writing 1 to this bit clears Channel 0 interrupts.

Yes/Clr

Channel 0 Done. Value of 1 indicates channel’s transfer is complete. Value of 0

indicates channel’s transfer is not complete.

Yes

7:5

Reserved.

Yes

4.6.12 (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register

Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register

Field

Description

Read

Write

Value after Reset

Channel 1 Enable. Value of 1 enables channel to transfer data. Value of 0 disables

channel from starting a DMA transfer and if in the process of transferring data

suspend transfer (Pause).

Yes

Channel 1 Start. Writing 1 to this bit causes channel to start transferring data if

channel is enabled.

Yes/Set

Channel 1 Abort. Writing 1 to this bit causes channel to abort the current transfer.

Channel enable bit must be cleared. Channel complete bit is set when the abort is

complete.

Yes/Set

Clear Interrupt. Writing 1 to this bit clears Channel 1 interrupts.

Yes/Clr

Channel 1 Done. Value of 1 indicates this channel’s transfer is complete. Value of 0

indicates channel’s transfer is not complete.

Yes

7:5

Reserved.

Yes

4.6.13 (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register

Same as Mode/Arbitration Register (MARBR) at address (PCI:08h)(LOC:88h) (refer to Table 4-35).

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