PCI9060ES datasheet(116/192 Pages) ETC

116 / 192 page

SECTION 8

PCI 9080

TIMING DIAGRAMS

©PLX Technology, Inc., 1997

Page 107

Version 1.02

C Mode Direct Master

Timing Diagram 8-30. (C Mode) Local Bus Read from PCI 9080 CFG Registers

Timing Diagram 8-31. (C Mode) Local Bus Write to PCI 9080 CFG Registers

Timing Diagram 8-32. (C Mode) Local Bus Direct Master Single Memory Read

Timing Diagram 8-33. (C Mode) Local Bus Direct Master Single Memory Write Cycle

Timing Diagram 8-34. (C Mode) PCI 9080 Direct Master Memory Read, 12 Lword Burst

Timing Diagram 8-35. (C Mode) PCI 9080 Direct Master Memory Write of 12 Lwords

Timing Diagram 8-36. (C Mode) PCI 9080 Direct Master Memory Read with WAITI#

Timing Diagram 8-37. (C Mode) PCI 9080 Direct Master Memory Write with WAITI#

Timing Diagram 8-38. (C Mode) PCI 9080 Direct Master Configuration Read—Type 1 or Type 0

Timing Diagram 8-39. (C Mode) PCI 9080 Direct Master Configuration Write—Type 1 or Type 0

Timing Diagram 8-40. (C Mode) Local Bus Direct Master Read from PCI I/O

Timing Diagram 8-41. (C Mode) Direct Master Write to PCI I/O

Timing Diagram 8-42. (C Mode) PCI 9080 Direct Master Memory Read—Keep Bus

Timing Diagram 8-43. (C Mode) PCI 9080 Direct Master Memory Read—Drop Bus

Timing Diagram 8-44. (C Mode) PCI Bus Request (REQ#) Delay During Direct Master Write (8 PCI Clock Delay)

Timing Diagram 8-45. (C Mode) Direct Master Memory Read, Prefetch of 16

Timing Diagram 8-46. (C Mode) Direct Master Memory Write and Invalidate (MWI)—Cache Line Size of 8

Timing Diagram 8-47. (C Mode) Direct Master in BIGEND Local Bus with BIGEND# Input or Interrupt

Timing Diagram 8-48. (C Mode) Direct Master Burst, Memory Read Cycles (Changing LBE[3:0]#)

Timing Diagram 8-49. (C Mode) Direct Master Five Lword Burst Write (Changing LBE[3:0]#)

Timing Diagram 8-50. (C Mode) Direct Master Locked Read Followed by Write and Release (LLOCK# and LOCK#)

Timing Diagram 8-51. (C Mode) BREQo and Deadlock

C Mode DMA

Timing Diagram 8-52. (C Mode) DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled

Timing Diagram 8-53. (C Mode) DMA Aligned Local Address to Aligned PCI Address, Bterm Enabled

Timing Diagram 8-54. (C Mode) DMA Aligned PCI Address to Aligned Local Address (External Generation of Wait States)

Timing Diagram 8-55. (C Mode) Read of DMA Chaining Parameters from PCI and Local Buses

Timing Diagram 8-56. (C Mode) PCI 9080 DMA Read of Chaining Parameters from Local Bus

Timing Diagram 8-57. (C Mode) Read of DMA Chaining Parameters from PCI Bus (Local to PCI Transfer)

Timing Diagram 8-58. (C Mode) Single Cycle DMA Demand Mode PCI to Local

Timing Diagram 8-59. (C Mode) Multiple Cycle (Burst) DMA Demand Mode PCI to Local with No Wait States

Timing Diagram 8-60. (C Mode) DMA Demand Mode Terminated with BLAST# (Local to PCI)

Timing Diagram 8-61. (C Mode) DMA Local to PCI, Terminated with EOT[1:0]#

Timing Diagram 8-62. (C Mode) DMA PCI to Local, Terminated with EOT[1:0]#

Timing Diagram 8-63. (C Mode) DMA PCI to Local with Local Pause Timer and Local Latency Timer

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