MC9S08DZ96F2CLL datasheet(185/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

185

8.5

Initialization / Application Information

This section describes how to initialize and conﬁgure the MCG module in application. The following

sections include examples on how to initialize the MCG and properly switch between the various available

modes.

8.5.1

MCG Module Initialization Sequence

The MCG comes out of reset conﬁgured for FEI mode with the BDIV set for divide-by-2. The internal

reference will stabilize in tirefst microseconds before the FLL can acquire lock. As soon as the internal

reference is stable, the FLL will acquire lock in tﬂl_acquire milliseconds.

NOTE

If the internal reference is not already trimmed, the BDIV value should not

be changed to divide-by-1 without ﬁrst trimming the internal reference.

Failure to do so could result in the MCU running out of speciﬁcation.

8.5.1.1

Initializing the MCG

Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched

to upon reset are FEE, FBE, and FBI modes (see Figure 8-9). Reaching any of the other modes requires

ﬁrst conﬁguring the MCG for one of these three initial modes. Care must be taken to check relevant status

bits in the MCGSC register reﬂecting all conﬁguration changes within each mode.

To change from FEI mode to FEE or FBE modes, follow this procedure:

1. Enable the external clock source by setting the appropriate bits in MCGC2.

2. If the RANGE bit (bit 5) in MCGC2 is set, set DIV32 in MCGC3 to allow access to the proper

RDIV values.

3. Write to MCGC1 to select the clock mode.

— If entering FEE mode, set RDIV appropriately, clear the IREFS bit to switch to the external

reference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the

system clock source.

— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS

bits to %10 so that the external reference clock is selected as the system clock source. The

RDIV bits should also be set appropriately here according to the external reference frequency

because although the FLL is bypassed, it is still on in FBE mode.

— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is

useful if the application will switch back and forth between internal and external modes. For

minimum power consumption, leave the internal reference disabled while in an external clock

mode.

4. Once the proper conﬁguration bits have been set, wait for the affected bits in the MCGSC register

to be changed appropriately, reﬂecting that the MCG has moved into the proper mode.

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