MC9S08DZ96F2CLL datasheet(62/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

When the MMU detects that the CPU is addressing the Paging Window, the value currently in PPAGE will

be used to create an extended address that the MCU’s decode logic will use to select the desired FLASH

location. For example, the Flash from location 0x4000-0x7FFF can be accessed directly or using the

paging window, PPAGE = 1, address 0x8000-0xBFFF.

4.4.2.2

CALL and RTC (Return from Call) Instructions

CALL and RTC are instructions that perform automated page switching when executed in the user

program. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere

in the normal 64K address space or on any page of program memory.

During the execution of a CALL instruction, the CPU:

•

Stacks the return address.

•

Pushes the current PPAGE value onto the stack.

•

Writes the new instruction-supplied PPAGE value into the PPAGE register.

•

Transfers control to the subroutine of the new instruction-supplied address.

This sequence is not interruptible; there is no need to inhibit interrupts during CALL execution. A CALL

can be executed from any address in memory to any other address.

The new PPAGE value is provided by an immediate operand in the instruction along with the address

within the paging window, 0x8000-0xBFFF.

RTC is similar to an RTS instruction.

The RTC instruction terminates subroutines invoked by a CALL instruction.

During the execution of an RTC instruction, the CPU:

•

Pulls the old PPAGE value from the stack and loads it into the PPAGE register

•

Pulls the 16-bit return address from the stack and loads it into the PC

•

Resumes execution at the return address

This sequence is not interruptible; there is no need to inhibit interrupts during RTC execution. An RTC

can be executed from any address in memory.

4.4.2.3

Data Space

The linear address pointer registers, LAP2:LAP0 along with the linear data register allow the CPU to read

or write any address in the extended FLASH memory space. This linear address pointer may be used to

access data from any memory location while executing code from any location in extended memory,

including accessing data from a different PPAGE than the currently executing program.

To access data using the linear address pointer, the user would ﬁrst setup the extended address in the 17-bit

address pointer, LAP2:LAP0. Accessing one of the three linear data registers LB, LBP and LWP will

access the extended memory location speciﬁed by LAP2:LAP0. The three linear data registers access the

memory locations in the same way, however the LBP and LWP will also increment LAP2:LAP0.

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