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MC9S08DZ96F2CLL bảng dữ liệu(PDF) 43 Page - Freescale Semiconductor, Inc |
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MC9S08DZ96F2CLL bảng dữ liệu(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 458 page ![]() Chapter 3 Modes of Operation MC9S08DZ128 Series Data Sheet, Rev. 1 Freescale Semiconductor 43 clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop3 Mode ” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Peripheral Mode Stop2 Stop3 CPU Off Standby RAM Standby Standby FLASH/EEPROM Off Standby Parallel Port Registers Off Standby ACMP Off Optionally On1 1 Requires the LVD to be enabled, else in standby. ADC Off Optionally On2 2 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IIC Off Standby MCG Off Optionally On3 3 IRCLKEN and IREFSTEN set in MCGC1, else in standby. MSCAN Off Standby RTC Optionally On4 4 Requires the RTC to be enabled, else in standby. Optionally On4 SCI Off Standby SPI Off Standby TPM Off Standby Voltage Regulator Optionally On5 5 Requires the LVD or BDC to be enabled. Optionally On5 XOSC Off Optionally On6 6 ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. I/O Pins States Held States Held |
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