MC9S08DZ96F2CLL datasheet(25/458 Pages) FREESCALE

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Chapter 1 Device Overview

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

1.3

System Clock Distribution

Figure 1-2 shows a simpliﬁed clock connection diagram. Some modules in the MCU have selectable clock

inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module

function.

The following are the clocks used in this MCU:

•

BUSCLK — The frequency of the bus is always half of MCGOUT.

•

LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules.

•

MCGOUT — Primary output of the MCG and is twice the bus frequency.

•

MCGLCLK — Development tools can select this clock source to speed up BDC communications

in systems where BUSCLK is conﬁgured to run at a very slow frequency.

•

MCGERCLK — External reference clock can be selected as the RTC clock source. It can also be

used as the alternate clock for the ADC and MSCAN.

•

MCGIRCLK — Internal reference clock can be selected as the RTC clock source.

•

MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPMx.

•

TPM1CLK — External input clock source for TPM1.

•

TPM2CLK — External input clock source for TPM2.

•

TPM3CLK — External input clock source for TPM3.

Figure 1-2. System Clock Distribution Diagram

TPM1

TPM2

IIC1

SCI1

SCI2

BDC

CPU

ADC

MSCAN

FLASH

MCG

MCGOUT

÷2

BUSCLK

MCGLCLK

MCGERCLK

COP

* The ﬁxed frequency clock (FFCLK) is internally

synchronized to the bus clock and must not exceed one half

of the bus clock frequency.

FLASH and EEPROM

have frequency

requirements for program

and erase operation. See

the electricals appendix

for details.

ADC has min and max

frequency requirements.

See the ADC chapter

and electricals appendix

for details.

XOSC

EXTAL

XTAL

EEPROM

SPI1

FFCLK*

MCGFFCLK

RTC

1 kHZ

LPO

TPM1CLK TPM2CLK

MCGIRCLK

÷2

TPM3

TPM3CLK

IIC2

SPI2

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